FM-OPLN FACE Module incorporates dual SFP+ fiber optics sockets providing LAN 10/100/1000BASE-T Ethernet connectivity, compliant with IEEE 802.3/u/ab standard, and two additional USB2.0 downstream ports.
Refer to Compatibility Matrix for products fit.
- 2x fiber optics SFP+ GbE LAN 10/100/1000BASE-T compliant with IEEE 802.3/u/ab
- 2x USB2.0 downstream ports, up to 480Mbps half-duplex
The following section provides information about FM-XTDEU2/4 main components and features.
Intel I210IS GbE Controller Intel Ethernet I210 controller is a single port, compact, low power component that supports GbE designs. The I210 offers a fully-integrated GbE Media Access Control (MAC), Physical Layer (PHY) port and supports PCI Express 2.1 (5GT/s). The I210 enables 1000BASE-T implementations using an integrated PHY. It can be used for server system configurations such as rack mounted or pedestal servers, in an add-on NIC or LAN on Motherboard (LOM) design. Another possible system configuration is for blade servers as a LOM or mezzanine card. It can also be used in embedded applications such as switch add-on cards and network appliances. One independent interface is used to connect the I210 port to external devices. The following protocol is supported: MDI (copper) support for standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab).
- PCIe v2.1 (5 GT/s) x1, with Switching Voltage Regulator (iSVR)
- Integrated Non-Volatile Memory (iNVM)
- Platform Power Efficiency
- IEEE 802.3az Energy Efficient Ethernet (EEE)
- Proxy: ECMA-393 and Windows logo for proxy offload
- Jumbo frames
- Interrupt moderation, VLAN support, IP checksum offload
- RSS and MSI-X to lower CPU utilization in multi-core systems
- Advanced cable diagnostics, auto MDI-X
- ECC – error correcting memory in packet buffers
- Four Software Definable Pins (SDPs)
Pericom PI6C20400 1-to-4 Differential Clock Driver Pericom Semiconductor's PI6C20400 is a high-speed, low-noise differential clock driver/buffer compatible with CML and HCSL differential I/O technology. The device distributes a differential input clock to four differential pairs of clock outputs either with or without PLL. The clock outputs are controlled by input selection of several static control signals and Host SMBus interface. The device oriented and designed for PCI Express applications.